Datta Receives VLSI Technology and Circuits Test of Time Award

Suman Datta has received the Test of Time Award at the 2022 IEEE Symposium on VLSI Technology and Circuits. Datta is the Joseph M. Pettit Chair in Advanced Computing in the Georgia Tech School of Electrical and Computer Engineering (ECE) and a Georgia Research Alliance Eminent Scholar.

Datta, who holds a joint appointment with the School of Materials Science and Engineering, was honored this year along with his co-authors and former colleagues at Intel Corporation for his 2006 research, “Tri-Gate Transistor Architecture with High-k Gate Dielectrics, Metal Gates and Strain Engineering.” True to its name, the Test of Time Award recognizes papers that have established their significance in history by standing the test of time. The goal of the award is to honor impactful papers and promote their recognition in the Symposia’s community.

As transistor gets smaller, it gets harder to switch off the transistor effectively. In response, Datta and his former Intel colleagues formulated the Tri-Gate transistor technology that was first introduced commercially at the 22-nm technology node. The transistor architecture has scaled to the 5-nm node and remains the workhorse of all leading-edge logic technology.

The research was the first experimental demonstration of high-performance NMOS and PMOS Tri-gate transistors in which the channel strain, high-k gate dielectric, gate electrode work functions, epitaxial source-drain regions were co-optimized together with the fin dimensions (width and height) and the fin shape (trapezoidal versus rectangular). The paper illustrated how to combine the electrostatic benefit of the fully-depleted nonplanar transistor structure with high-permittivity gate dielectric, work-function engineered metal gate electrodes and high- strain-engineered high-mobility channel to demonstrate high-performance CMOS transistors.

In addition to receiving the Test of Time Award at the symposium, Datta organized a short course on Monolithic and Heterogenous Integration and Advances in Application-Specific Computing Systems and Technologies. His research group presented three papers at the symposium on A Thousand State Superlattice Ferroelectric Field Effect Transistor Analog Weight Cell (with Professor Shimeng Yu); BEOL Compatible Ferroelectric Routers for Run-time Reconfigurable Compute-in-Memory Accelerators (with Professor Shimeng Yu) and Multi-bit per-cell 1T SiGe Floating Body RAM for Cache Memory in Cryogenic Computing (with Professor Arijit Raychowdhury).

Now in it’s 42nd year, the IEEE Symposium on VLSI Technology and Circuits is known as the microelectronics industry’s premiere international conference integrating technology, circuits, and systems. The 2022 symposium convened this year in Honolulu, Hawaii.