Michael Filler, associate director for research programs in Georgia Tech’s Institute for Electronics and Nanotechnology (IEN), was recently featured on the “Stories from the NNI” podcast. In the episode, Filler discusses balancing functionality and manufacturing scale during the process of making nanowires, his vision for on-demand nanoelectronics, and the benefits of interdisciplinary research.

When it comes to on-demand electronics, Filler and his team are working to develop a process that allows circuits to be built anywhere, without the need for expensive facilities.

“There are a lot of folks out there who have built on-demand platforms for circuit boards,” Filler explains. “But, in terms of nano, in terms of building chips in an on-demand fashion, we don’t have that technology.” Filler and his team are building a platform to do just that.

Listen to the entire podcast here.

Learn more about Filler’s work in the Filler Lab at Georgia Tech.

Hundreds of researchers gathered in Hilton Head, SC, from June 5-9, for the 2022 Hilton Head Solid-State Sensors, Actuators, and Microsystems Workshop. This was the 20^th meeting of the biennial event, which is known as one of the premier workshops for researchers to discuss recent advances in microelectromechanical systems (MEMS).

The workshop started in 1984 and draws attendees from academia, industry, and government organizations with diverse backgrounds in engineering and science. It opened to international attendees in 2020 and provides a forum for knowledge exchange and collaboration. This year’s theme was "Preparation and Prevention: Tackling our Grand Challenges."

Nine papers from Georgia Tech researchers in the Institute for Electronics and Nanotechnology (IEN) were accepted to the conference. The paper, A Microtip Equipped Bidirectional Microrobot for Navigating on and Penetrating a Leaf Surface, presented by Tony H. Wang, Dea Gyu Kim, Zhijian Hao, and Azadeh Ansari, won the Springer Nature Best Poster Award. In addition, the paper Wafer-Level High-Aspect-Ratio Deep Reactive Ion Etching of 4h-Silicon Carbide on Insulator Substrates presented by Ardalan Lotfi, Micheal P. Hardin, Zhenming Liu, Alex Wood, Chris Bolton, Kevin Riddell, Huma Ashraf, Joanne Carpenter, and Farrokh Ayazi, was one of two runners up in the category.

“I consider this the flagship North American conference for MEMS researchers,” said IEN Executive Director Oliver Brand. “It is a highly interactive workshop and a great opportunity for our graduate students to learn about the newest research and mingle with their peers from the top MEMS research groups across the country.”

In addition to Georgia Tech’s strong presence in paper presentations, IEN Principal Research Scientist Paul Joseph ran a National Nanotechnology Coordinated Infrastructure (NNCI) booth to spread the word about the initiative, which the National Science Foundation funds. Ansari, Brand, Ayazi, and Nima Ghalichechian also served on the local organizing committee, and IEN sponsored the workshop.

The other papers presented at the workshop are listed below:

Power Handling Challenges of High K_T² AlScN Lamb Wave Resonators
Mingyo Park, Yue Zheng, and Azadeh Ansari

Exploiting Nonlinear Properties of VO₂ in a mmWave Antenna-Coupled Sensor
Shangyi Chen, Mark Lust, and Nima Ghalichechian

A High-Q Solid Disk BAW Gyroscope in Monocrystalline 4h Silicon-Carbide with Sub-PPM As-Born Frequency Split
Zhenming Liu, Ardalan Lotfi, Michael P. Hardin, and Farrokh Ayazi

Utilization of Varying Transient Response Times in Gravimetric and Impedimetric Multivariate Gas Sensor with Single Polymeric Sensing Film for Enhanced Selectivity
Steven A. Schwartz, Luke A. Beardslee, and Oliver Brand

An Out-of-Plane Wide Bandwidth Micro-G FM Accelerometer with Differential Output
Seungyong Shin, Tanya Chauhan, Justin Matthews, Haoran Wen, and Farrokh Ayazi

Enhancement of Q and K² in AL_0.8SC_0.2N/GAN/Sapphire Surface Acoustic Wave Resonators Using Semiconductor Ground Contact
Yue Zheng, Jialin Wang, Mingyo Park, Ping Wang, Ding Wang, Zetian Mi, and Azadeh Ansari

Piezoresistive Micro-Pillar Sensor for In-Plane Force Sensing for Biological Applications
Isha Lodhi, Durga Gajula, Devin K. Brown, Wilbur A. Lam, David R. Myers, and Oliver Brand

Learn more about the Hilton Head Workshop

Researchers at the Georgia Institute of Technology are developing a wideband four-channel millimeter wave transmit-receive (T/R) module based on silicon-germanium (SiGe) technology that will support active electronically-scanned arrays (AESA) for potential military applications.

Designed to operate between 18 GHz and 50 GHz, the module could help address threat systems operating at millimeter wave frequencies and provide to military applications many of the advantages that millimeter wave technology is bringing to commercial applications such as 5G wireless, internet-of-things devices, and radar-based vehicle collision avoidance systems.

“The goal is to demonstrate small size, weight, power, and cost in a wideband millimeter wave T/R module,” said Paul Jo, a Georgia Tech Research Institute (GTRI) research engineer who is leading the project. “This would be a major module at the front of the AESA system, right behind the radiator element to process signals.”

Known as Millimeter Wave Active Electronically Scanned Array using Silicon-Germanium Transmit/Receive Modules (MAESTRO), the project represents a collaboration of GTRI and SiGe specialists in Georgia Tech’s School of Electrical and Computer Engineering. The use of SiGe helps support the high level of integration necessary for the miniaturization required by the module’s high-frequency operation.

“When it comes to millimeter wave frequencies, the AESA element lattice is less than one centimeter in size, and at 50 GHz, it’s three millimeters, which is very challenging to work with,” Jo noted. “That forces an extreme level of integration and miniaturization for this T/R system, which we are addressing through design and fabrication of the small SiGe monolithic microwave integrated circuit (MMIC) die.”

The researchers recently completed the fabrication and packaging of a core channel T/R module die, and are designing an evaluation board to demonstrate performance of the module. Also completed is the fabrication of a stand-alone radiator board for wideband and high-frequency applications; that evaluation board also is under test.

Wideband AESAs are an enabling technology for current and future military radar and communications systems by providing rapid beam steering, graceful degradation, electronic production, and low probability of intercept. The atmospheric attenuation of radio-frequency (RF) signals at millimeter wave frequencies is much greater than at microwave frequencies. As a result, high-gain directional apertures such as AESAs are required to propagate energy over tactically relevant distances.

Beyond the high level of integration, the system presents technical challenges related to manufacturing, packaging, and thermal management. For packaging MAESTRO, the research team is evaluating a Flip-Chip Ball Grid Array (FCBGA) solution to reduce the signal path from the die to the printed circuit board.

Earlier in the four-year project, the research team designed and fabricated single-channel and four-channel T/R modules and measured the RF performance of a chip-on-board (CoB)-assembled single-channel T/R module. The measured results confirmed that the designed digital control circuitry works for both Tx and Rx modes – attenuation and true-time delay – and that the time delay was consistent across the target bandwidth.

The MAESTRO program is a collaboration between GTRI and the research team of John Cressler, a Regents Professor at the Georgia Tech School of Electrical and Computer Engineering. Cressler’s team specializes in SiGe for heterojunction bipolar devices designed to provide high-frequency performance in mixed-signal circuit and analog circuit ICs.

“Silicon is a standard technology that industry is using to integrate very complicated systems,” Jo noted. “Since we needed to integrate the whole T/R module system into a very small lattice spacing, we decided to use SiGe to integrate all the discrete components.”

During testing of the T/R module, the researchers realized that the receive mode of their system could operate at even lower frequencies – down to 5 GHz – giving it an operating range of 5 GHz to 50 GHz. Efforts are underway to expand the range of the transmit mode to accommodate a similarly wider frequency band.

The MAESTRO project is part of a GTRI initiative to use SiGe semiconductor technology for a variety of RF applications. The SiGe Multifunction IC for Radio Frequency (SMIRF) program is developing a wideband, multichannel, reconfigurable radio frequency transceiver integrated circuit using the SiGe technology. The goal is to enable element-level digital beamforming of an AESA for RF-converged multifunction systems to support concurrent operating modes such as radar, communications, electronic warfare, positioning, and signals intelligence (SIGINT).

MAESTRO has been supported by GTRI’s Independent Research and Development program.

Writer: John Toon (John.Toon@gtri.gatech.edu)

GTRI Communications

Georgia Tech Research Institute

Atlanta, Georgia USA

The Georgia Tech Research Institute (GTRI) is the nonprofit, applied research division of the Georgia Institute of Technology (Georgia Tech). Founded in 1934 as the Engineering Experiment Station, GTRI has grown to more than 2,800 employees, supporting eight laboratories in over 20 locations around the country and performing more than $700 million of problem-solving research annually for government and industry. GTRI's renowned researchers combine science, engineering, economics, policy, and technical expertise to solve complex problems for the U.S. federal government, state, and industry.

With his eighth and ninth papers published in this year’s IEEE International Symposium on High-Performance Computer Architecture (HPCA), Tushar Krishna has been inducted into the organization’s Hall of Fame. Only 10 members of the HPCA community were inducted to the Hall of Fame this year — a significant distinction reserved for researchers with eight or more papers appearing in the proceedings of the symposium.

The 28th HPCA Symposium took place virtually April 2-6, 2022, where Krishna, an associate professor in Georgia Tech’s School of Electrical and Computer Engineering (ECE), was honored. The Symposium is hosted by IEEE (Institute of Electrical and Electronics Engineers) and provides a high-quality forum for scientists and engineers to present their latest research findings in the rapidly changing field.

Krishna had two papers at HPCA 2022. The first was titled “MAGMA: An Optimization Framework for Mapping Multiple DNNs on Multiple Accelerator Cores”. ECE Ph.D. student Sheng-Chun Kao co-authored the paper. It presented a software scheduler for efficiently mapping multiple Deep Neural Networks (DNN) on emerging hardware platforms that include multiple AI accelerators. An AI Accelerator refers to specialized hardware optimized for running AI workloads.

The second paper, “Stay in your Lane: A NoC with Low-overhead Multi-packet Bypassing” was co-authored with collaborators from University of Toronto, Texas A&M University, and University of Wisconsin-Madison. It presented a technique for packets stuck at routers in networks on chip (NoC) due to congestion or deadlocks to progress to their destination via high-priority bypass paths.

His research team in Synergy Lab at Georgia Tech won the Best Paper Award at the 26th HPCA Symposium in 2020. The team’s award-winning paper, "SIGMA: A Sparse and Irregular GEMM Accelerator with Flexible Interconnects for DNN Training,” showcased SIGMA, a flexible and scalable AI Accelerator that offers high utilization of all its processing elements for Deep learning (DL) — the premier algorithmic technique for analyzing data across multiple domains, especially in visual understanding, speech perception, and automated reasoning.

Krishna has been an ECE faculty member since 2015 with an adjunct appointment in the School of Computer Science. He held the ON Semiconductor Junior Professorship in ECE from 2019-2021. He serves as an associate director for the Center for Research into Novel Computing Hierarchies (CRNCH). Krishna’s research spans computer architecture, interconnection networks, networks-on-chip (NoC), and deep learning accelerators – with a focus on optimizing data movement in modern computing systems. His research is funded via multiple awards from NSF, DARPA, IARPA, Department of Energy, Intel, Google, Facebook, Qualcomm and TSMC. His papers have been cited over 11,000 times. Three of his papers have been selected for IEEE Micro’s Top Picks from Computer Architecture, one more received an honorable mention, and four have won best paper awards. He received the “Class of 1940 Course Survey Teaching Effectiveness” Award from Georgia Tech in 2018 and the “Roger P. Webb Outstanding Junior Faculty Award” from the School of ECE in Georgia Tech in 2021.