Suresh Sitaraman

Suresh Sitaraman is a Professor in the George W. Woodruff School of Mechanical Engineering, and leads the Flexible Hybrid Electronics Initiative at Georgia Tech and directs the Computer-Aided Simulation of Packaging Reliability (CASPaR) Lab at Georgia Tech. He is a Thrust Leader/Faculty Member, Reliability/Mechanical Design Research, 3D Systems Packaging Research Center; a Faculty Member, Georgia Tech Manufacturing Institute; a Faculty Member, Interconnect and Packaging Center, an SRC Center of Excellence, Institute for Electronics and Nanotechnology; a Faculty Member, Nanoscience and Nanotechnology, Nanotechnlogy Research Center, Institute for Electronics and Nanotechnology; a Faculty Member, Institute of Materials. Dr. Suresh Sitaraman's research is exploring new approaches to develop next-generation microsystems. In particular, his research focuses on the design, fabrication, characterization, modeling and reliability of micro-scale and nano-scale structures intended for microsystems used in applications such as aerospace, automotive, computing, telecommunicating, medical, etc. Dr. Sitaraman's research is developing physics-based computational models to design flexible as well as rigid microsystems and predict their warped geometry and reliability. His virtual manufacturing tools are able to simulate sequential fabrication and assembly process mechanics to be able to enhance the overall yield, even before prototypes are built. Dr. Sitaraman's work is developing free-standing, compliant interconnect technologies that can mechanically decouple the chip from the substrate without compromising the overall electrical functionality. This work is producing single-path and multi-path interconnect technologies as well as nanowire and carbon nanotube interconnects for electrical and thermal applications, and such interconnect technologies can be employed in flexible as well as 3D microelectronic systems. Dr. Sitaraman's research is also developing innovative material characterization techniques such as the stressed super layer technique as well as magnetic actuation test that can be used to study monotonic and fatigue crack propagation in nano- and micro-scale thin film interfaces. In addition, Dr. Sitaraman has developed fundamental modeling methodologies combined with leading-edge experimentation techniques to study delamination in the dielectric material and copper interface used in back-end-of-the-line (BEOL) stacks and through-silicon vias as well as epoxy/copper and epoxy/glass interfaces as in microelectronic packaging and photovoltaic module applications. Examining the long-term operational as well as accelerated thermal cycling reliability of solder interconnects, his work has direct implications in implantable medical devices, photovoltaic modules, computers and smart devices as well as rugged automobile and aerospace applications. Through the above-mentioned fundamental and applied research and development pursuits, Dr. Sitaraman's work aims to address some of the grand challenges associated with clean energy, health care, personal mobility, security, clean environment, food and water, and sustainable infrastructure